module extender (
	input [31:0] inst,
	input [2:0] op_ext,
	output reg signed [31:0] imm
);

    wire signed [31:0] imm_I, imm_U,imm_B,imm_S, imm_J;
    assign imm_I = { {20{inst[31]}}, inst[31:20]};
	assign imm_U = { inst[31:12], 12'b0};
	assign imm_S = { {20{inst[31]}}, inst[31:25], inst[11:7]};
	assign imm_B = { {20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0}; // default pc+1
    assign imm_J = { {12{inst[31]}}, inst[19:12], inst[20], inst[30:21], 1'b0};
    
	always @ (*) begin
		case(op_ext)
			0: imm = imm_I;
			1: imm = imm_U;
			2: imm = imm_S;
			3: imm = imm_B;
			4: imm = imm_J;
			default: imm = 0;
		endcase
	end
endmodule